The present invention relates to a temperature detecting circuit and particularly to a temperature detecting circuit for controlling a self-refresh period of a semiconductor memory device.
A dynamic random access memory (hereinafter called “DRAM”) stores data by storing an electric charge in a memory cell capacitor. As time passes, the electric charge stored in that capacitor leaks through a substrate or the like, making it difficult to permanently store data. It is, therefore, necessary to perform a refresh operation, that is, continuously rewrite the data at a pre-determined interval.
Generally, the refresh operation is achieved by applying an external control signal. A refresh operation which is achieved by an internal control signal generated inside the memory is called a “self-refresh function.”
With the recent expansion of applications for DRAM, the demand for DRAM for use with devices or equipment with a battery-backup function has increased. Thus, it is desirable that DRAMs have a self-refresh function that requires minimal power.
As a typical example of a conventional DRAM with a self-refresh function, a prior art DRAM as illustrated in Electronic Information and Communication Society, Technical and Research Report, Vol. 91, No. 64, (SDM91-10-22), pp. 51-57, is described with reference to FIG. 1 showing a circuit concept diagram and FIG. 2 showing a signal waveform diagram.
The operation of the DRAM is described briefly as follows.
A precharge signal OP precharges 1 k bit dummy memory cells. When this occurs, φE assumes logic level “H” to enable a timer which generates a time T1. A refresh operation is carried out a predetermined number of times (NCYC) during the period T1. Thereafter, the signals φP, φE are reset to logic level “L.” Once the signals have been reset, the charge at node VN of the dummy memory cell begins leaking. When the voltage at node VN reaches a reference level VREF, φE and φP assume logic level “H” again. Then, the above mode of operation is repeated. The period of time where leaking is seen at node VN is called “self-refresh interval”. However, when the temperature is lower, the self-refresh function in a DRAM experiences a prolonged self-refresh interval.
Consumption current I of DRAMs during refresh may be represented as shown below where IAC is consumption current under enabled condition and IDC is one under standby (not-enabled) condition:I=IAC/T+IDCThe consumption current I during refresh decreases as the refresh interval T becomes longer.
The conventional DRAM having a self-refresh function utilizes the temperature dependency of the leak speed of the charges stored in the dummy memory cells in order to reduce the consumption current at low temperatures to a minimum by extending the self-refresh interval with low temperatures.
FIG. 3 illustrates the relationship of the self-refresh interval during the self-refresh function and the data hold time of a DRAM in regard to temperature. The data hold time of memory cells of DRAMs is determined by the data hold time of the memory cell which assumes the shortest data hold time, out of a number of the memory cells. When temperature increases, the data hold time of some of the memory cells becomes very short. As shown in FIG. 3, in some instances, the temperature dependency of the data hold time is larger than that of the self-refresh interval.
Japanese Patent Laid-open 3-207084 discloses a dynamic random access memory device having a refresh interval which is variable with the ambient temperature. This device is described with reference to FIG. 4. Resistor R1 and variable resistor VR1 are connected in series between power supply voltage VCC and a ground level. Similarly, resistors R2, R3, R4 are connected between the power supply voltage VCC and ground level. A signal at the junction of the resistors R2, R3 is supplied to two comparators 41 and 42. A signal at the junction of the resistors R2, R3 is supplied to the comparator 41 via node N1, whereas a signal at the junction of the resistors R3, R4 is supplied to the comparator 2 via node N2. Outputs of the comparators 41 and 42 are represented as S1, S2. A detector 3 is suggested which uses the output S1 at 60° C. as a detection signal and the output S2 at 40° C. as a detection signal.
FIG. 5 illustrates a MOS transistor temperature detecting circuit as disclosed in U.S. Pat. No. 5,095,227. A p-channel MOS transistor M5 operated in the subthreshold region is used as a current supply 510. The source of the P-channel MOS transistor M5 is connected to the first power supply line 511, the drain of M5 is connected to a third node N3, and the gate M5 is connected to a current setting circuit 530 through node N2. One terminal of the polycrystalline silicon resistor 520 is connected to the third node N3, and the other terminal is connected to the second power supply line 512. The current setting circuit 530 includes two p-channel MOS transistors and two n-channel MOS transistors. The source of a first p-channel MOS transistor M1 is connected to the first power supply line 511; the gate is connected to the second power supply line 512; and the drain is connected to the first node N1. The drain current ID1 of M1 supplies the first node N1. The drain and gate of a second n-channel MOS transistor M2 are commonly connected to the first node N1, and the source is connected to the second power supply line 512. The ratio between the geometrical sizes of the first and second MOS transistors is to satisfy the formula, W1<<W2 (L1-L2), so that the second MOS transistor M2 should be operable in the subthreshold region. The M2 transistor is geometrically larger than the M1 transistor. The drain of a third n-channel MOS transistor M3 is connected to the second node N2; the source is connected to the second power supply line 512; and the gate is connected to the first node N1 so that it should have the same bias voltage as that of the second MOS transistor. Accordingly, the third MOS transistor M3 is operable in the subthreshold region regardless of the channel width thereof. The M3 transistor is geometrically smaller than the M2 transistor. The gate and drain of a fourth p-channel MOS transistor M4 are commonly connected to the second node N2, and the source of it is connected to the first power supply line 511. The ratio between the geometrical sizes of the third and fourth MOS transistors M3, M4 satisfies the formula W3<<W4(L3-L4), so that the said fourth MOS transistor M4 should be operable in the subthreshold region. The M4 transistor is geometrically larger than the M3 transistor. The gate of p-channel MOS transistor M5 of current supply 510 is connected to the gate of the fourth MOS transistor M4. Accordingly, M5 is made to have the same gate voltage as that of the fourth MOS transistor M4, such that M5 is made operable in the subthreshold region. The ratio between the geometrical sizes of the fourth and fifth MOS transistors M4, M5, satisfies the formula W4>>W5(L4-L5). The drain of the fifth MOS transistor has a negligible amount of current compared with the drain current of the first MOS transistor, especially in light of the geometrical sizes of the second to fifth MOS transistors. Also, the current supply is not affected by temperature variation and the method of manufacturing. The output voltage VO can be defined by the following formula:VO=ID5×RT(K)
where RT(K) represents the resistance values of the polycrystalline silicon for different temperature levels.
A conventional temperature detecting circuit is shown in FIG. 6. The circuit is composed of a CMOS type differential amplifier and voltage dividers of resistors which generate the input signals to the amplifier. The resistors used are formed of N-well and Poly-Si. FIG. 7 is a timing diagram for the detecting circuit shown in FIG. 6.
However, conventional temperature detecting circuits must be activated by control signals. Further, one temperature detecting circuit is used to detect only one of the predetermined temperatures where transition of the refresh rate is triggered. Thus, more than one circuit must be used if there are several transition temperatures of the refresh rate. This increases the layout area and complexity of the refresh controller in a DRAM.